Product Operation CLOCK and Knowledge TRANSITIONS

The SDA pin is generally pulled higher by having an exter- nal machine. Information within the SDA pin may change only all through SCL low time periods (check with Details Validity timing diagram). Info changes all through SCL higher intervals will indicate a start out or stop problem as defined below.

Start out Situation: A high-to-low transition of SDA with SCL higher is usually a start off issue which must precede almost every other command (confer with Begin and Cease Definition timing diagram).

Stop Issue: A low-to-high changeover of SDA with SCL large is a stop affliction. Following a examine sequence, the quit command will location the EEPROM in a very standby ability manner (check with Get started and End Definition timing diagram).

Admit: All addresses and info words are serially transmitted to and in the EEPROM in eight bit words. The EEPROM sends a zero to acknowledge that it's got received each and every phrase. This happens throughout the ninth clock cycle.

STANDBY Mode: The AT24C02A/04A/08A/16A features a lower ability standby manner that's enabled: (a) on power-up and (b) immediately after the receipt of the End little bit as well as the completion of any inside operations.

MEMORY RESET: Right after an interruption in protocol, electrical power decline or technique reset, any 2-wire portion could be reset by next these actions: (a) Clock up to 9 cycles, (b) seem for SDA large in just about every cycle whilst SCL is higher after which you can (c) produce a start out affliction as SDA is superior.