OK! So let's go over and sketch a layout.... I note this term might here 2k par square...
and sketch the layout in this process...
and here is my nicely layout....all right....I got a layout here......
let's say this width is a 10.....let's say this length is ....ah..let's say...300.
This is N-well...so...to begin with....I want you to tell me how many squares of N-well do I have ?...(30...)
Year! for each one ..... to ten by ten....
I've got thirty of those square so I could have also done this..... L over W equals...300 over 10...it's equals
equals 30 □.that supposed to be a square.
I commented either over all resistances equal 2k times 30(300?) over 10.....or
two k ktimes(?) over 40 over 40 equal two...(?)
equals 60k ! this is a nominal value.
so even though I've got my current my ....through ...???pattern
I still getting a process in a resistance side using that 60k there...
and amm.....It's an estimate resistance I would see a ±10 to 20 % variation in a sheet resistance...
that's one of home work I promiss I'll talk about later.Here are their any questions on calculating the resistance here ?
One more thing important let's you look at is a resistance of a corner....
When you have a corner generally we'll put this 0.6□ when you are calculating over all resistance.
....because the current that flow through here flow through less material than a .current flowing out here ...
you get less resistance at the corner only ...0.6 .....you need to do that....
when you do the part 2 layout of home work on Monday.... cause those surpentin pattern ....
looks like this ...you know ...lots of corner.... estimate for a sheet resistance...
...Yes...(one more question ....Is that 0.6 times resistivity ? ) No no..no you just treat it 0.6□.
I'm going example ...let's say that I've got a square here...square here....and a square here....
and I ask what's the resistance between the two ?
So here is one square here's one square and here's 0.6 and so between here and here I get 2.6□.
(there is 0.6 ?)
instead of one ?
(Yeah...)
Because it's remember the current flows like this or here current flow right through one edge that are parallel...
here is the current through over so here is less material and lower resistance what's going over here.
(......mathematically..... ?)
Oh yeah that provably is...Jenny is OK exactlly about resistor...
because this is a sheet resistance is varied
OK any question about sheet resistances or calculating of the resistor value ?
OK...I need to go quick example...we got about ....8 minutes.
Let's one more quick example here....
I layout a resistor and ah...here's my resistor...
and I put on one side ...put one volt
and let's assume minus one volt so what's the voltage drop across the resistor ?
(2 ....) 2 volts? and I ask you what's the issue ?
so here's my N-well ....this side -1 and this side +1.....
(....) Yeah when I draw a cross section...this is a way I'm thinking ..so I don't wanna think it just a resistor...
I wanna think what's happening in the layout and a parasitic.... I end up getting ...
..draw my little diode on here.......
If my substrate is a ground....and one side -1 volt the other side +1 volt...well now......
what do I do if it's diode ... I forward biased diode and I get a huge current flow through this side....
so that's a really behave like a resistor...behave like a resistor and a diode a parasitic there.
We need to do charge pump.....We need to do design a charge pump....
which is.... the circuit.... that generate the voltage..without five ...plucks of supply rail
so we are easy to forget what's happening here and you end up getting a situation
where you ....forward biased parasitic. OK ?
All right ....Any questions on that ? I wanna cover one more thing quick
we've got seven minutes....which is very important ....I wanna just end it up today....
depletion region and depletion capacitance.
....OK...
So....the other thing .....parasitic
that's involved with this N-well here.....yes we know that's resistance associate with any semiconductor here.....
we know there's parasitic diode....there's also parasitic capacitance resulted from depletion capacitance
between N-well and the p-substrate...
So we want it discuss that depletion capacitance and... understand how it affect our resistance.....
cause well ...we're gonna find it that or large reverse biases the depletion region actually depend on
side resister ....it end up with reducing the thickness that the resistor has.
and that's increasing the resistance...so by applying a different voltaged we multi lay the thickness
of the depletion region there...and we change the resistance of the resistor.
Now ...there's another important thing when you are doing presision designs again.....
All this ...drawing a Box on the N-well layer...
All right so....let's talk about depletion region....
OK ! So !
In that region I've got a type of material which is let's say here which is N-type........
and in your mind when I say N-type ....you think of excess what ??
(...) Yeah! electron . That electron introduced atom....borron with the silicon has
one left over the electron...and causes when I dope n-type .....causes resistivity........
causes the sheet resistance to do what ? .....decrease .....and adding more electron....
the resistance decreases because I got more electron they notice tightly coupled to this..... six atoms
.........it's easier for them to move around... resistance goes down increasing the doping concentration...
the resistace goes down. OK.
What is electrically.....what is just in this material right here....electrically........it's what ?
Is it got a positive charge because it's n-type ...the negative charge ? what ?
It's neutral !
That's an important thing..... Just because it has ....electron
that has freedom to move around.that has meaning the net negative charge....
electrically neutral so every one of those electron I've got an atom or a nucleus there ....
with an equal oposite positive charge make this material electrically neutral...
Now ...I do .... I just learn together for the moment...if I do p-type....
here we have excess holes and all we think of there is ...
that means there is a vacancy of electron where ?...in valence band.
There is no such thing as a hole.So electron we have electrons that are up in the conduction band...
that increase the conductivity or we have a vacancy or dc for a electron move in a vacancy in the valence band...
and that also....part of the sheet resistance to go down....for I introduce the material ....like a borron...
or from other material having three valence electron....into this area here...I have more open vacancy in my
crystal structure to electron free them move around and cause the resistivity also to decrease.
If I look at this ...it's also electrically neutral..
OK ! Now ...got .all of these hole over here all of these free hole ....got all of those free electron
when I put that too much area together some of the electron fall into the hole....wherein our electron
falls into a hole.....what it electrically behind on this side ?
It leaves behind fixed positively charged atom.
so ....leave behind fixed positive charge....
so this ends up all positive...(Micron : 4 minutes....)
OK...Over here now I'm gonna electron comming in I ends up causing this avenue electrically what ?
(....) Negative charge ....so we notice p-type electrically neutral over here....over here...I've got a negative charge...
over here...I've got a positive charge.
why don't all of the electron turn the n-type go over and fall into the hole on the p-side ?
(...) Yeah!....everytime I lose an electron here a fixed atoms left behind it...and there exisist an
electric field trying to pull that electrons back.....so they equalize the charge....
the thing we note here....is that when I lose my electron here and close up the hole over here ...
to deplete it over here electrons or the hole to deplete it free carriers here.....this is called depletion region
against(??) light two depletion capacitance and that's all we will talk about when we come back next time...
...there any last twenty second question ?
No?! all right see you for the quize of the begining of the class on Friday. Have a good one!
第四回めの講義はここまででした。
聴き取りは大変。
特に、自宅のPCの音声がつぶれかけていて余計わかりにくい・・・会社のPCはもっときれいな音声だった・・・
（ADSLなのでノイズが増えるのかもしれない？？それとも、VAIOのA/D、D/Aが低級なんだっけ？？？）
以上、ちょっと変態な作業でした・・・・
この後、同じＩＰでサーバーへのアクセスが出来なくなったので、まねはしませんように！
Jake Baker CMOS教科書
ネットレクチャーはこちら！Lecture notes and streaming videos をクリック！
基礎から固める人は↓
基礎から
Ｏｐアンプの設計から入る人は↓
詳しくアンプを設計
ディジタル信号処理の回路設計を知りたい人↓
Mixed Signal 設計
へそれぞれどうぞ！
and sketch the layout in this process...
and here is my nicely layout....all right....I got a layout here......
let's say this width is a 10.....let's say this length is ....ah..let's say...300.
This is N-well...so...to begin with....I want you to tell me how many squares of N-well do I have ?...(30...)
Year! for each one ..... to ten by ten....
I've got thirty of those square so I could have also done this..... L over W equals...300 over 10...it's equals
equals 30 □.that supposed to be a square.
I commented either over all resistances equal 2k times 30(300?) over 10.....or
two k ktimes(?) over 40 over 40 equal two...(?)
equals 60k ! this is a nominal value.
so even though I've got my current my ....through ...???pattern
I still getting a process in a resistance side using that 60k there...
and amm.....It's an estimate resistance I would see a ±10 to 20 % variation in a sheet resistance...
that's one of home work I promiss I'll talk about later.Here are their any questions on calculating the resistance here ?
One more thing important let's you look at is a resistance of a corner....
When you have a corner generally we'll put this 0.6□ when you are calculating over all resistance.
....because the current that flow through here flow through less material than a .current flowing out here ...
you get less resistance at the corner only ...0.6 .....you need to do that....
when you do the part 2 layout of home work on Monday.... cause those surpentin pattern ....
looks like this ...you know ...lots of corner.... estimate for a sheet resistance...
...Yes...(one more question ....Is that 0.6 times resistivity ? ) No no..no you just treat it 0.6□.
I'm going example ...let's say that I've got a square here...square here....and a square here....
and I ask what's the resistance between the two ?
So here is one square here's one square and here's 0.6 and so between here and here I get 2.6□.
(there is 0.6 ?)
instead of one ?
(Yeah...)
Because it's remember the current flows like this or here current flow right through one edge that are parallel...
here is the current through over so here is less material and lower resistance what's going over here.
(......mathematically..... ?)
Oh yeah that provably is...Jenny is OK exactlly about resistor...
because this is a sheet resistance is varied
OK any question about sheet resistances or calculating of the resistor value ?
OK...I need to go quick example...we got about ....8 minutes.
Let's one more quick example here....
I layout a resistor and ah...here's my resistor...
and I put on one side ...put one volt
and let's assume minus one volt so what's the voltage drop across the resistor ?
(2 ....) 2 volts? and I ask you what's the issue ?
so here's my N-well ....this side -1 and this side +1.....
(....) Yeah when I draw a cross section...this is a way I'm thinking ..so I don't wanna think it just a resistor...
I wanna think what's happening in the layout and a parasitic.... I end up getting ...
..draw my little diode on here.......
If my substrate is a ground....and one side -1 volt the other side +1 volt...well now......
what do I do if it's diode ... I forward biased diode and I get a huge current flow through this side....
so that's a really behave like a resistor...behave like a resistor and a diode a parasitic there.
We need to do charge pump.....We need to do design a charge pump....
which is.... the circuit.... that generate the voltage..without five ...plucks of supply rail
so we are easy to forget what's happening here and you end up getting a situation
where you ....forward biased parasitic. OK ?
All right ....Any questions on that ? I wanna cover one more thing quick
we've got seven minutes....which is very important ....I wanna just end it up today....
depletion region and depletion capacitance.
....OK...
So....the other thing .....parasitic
that's involved with this N-well here.....yes we know that's resistance associate with any semiconductor here.....
we know there's parasitic diode....there's also parasitic capacitance resulted from depletion capacitance
between N-well and the p-substrate...
So we want it discuss that depletion capacitance and... understand how it affect our resistance.....
cause well ...we're gonna find it that or large reverse biases the depletion region actually depend on
side resister ....it end up with reducing the thickness that the resistor has.
and that's increasing the resistance...so by applying a different voltaged we multi lay the thickness
of the depletion region there...and we change the resistance of the resistor.
Now ...there's another important thing when you are doing presision designs again.....
All this ...drawing a Box on the N-well layer...
All right so....let's talk about depletion region....
OK ! So !
In that region I've got a type of material which is let's say here which is N-type........
and in your mind when I say N-type ....you think of excess what ??
(...) Yeah! electron . That electron introduced atom....borron with the silicon has
one left over the electron...and causes when I dope n-type .....causes resistivity........
causes the sheet resistance to do what ? .....decrease .....and adding more electron....
the resistance decreases because I got more electron they notice tightly coupled to this..... six atoms
.........it's easier for them to move around... resistance goes down increasing the doping concentration...
the resistace goes down. OK.
What is electrically.....what is just in this material right here....electrically........it's what ?
Is it got a positive charge because it's n-type ...the negative charge ? what ?
It's neutral !
That's an important thing..... Just because it has ....electron
that has freedom to move around.that has meaning the net negative charge....
electrically neutral so every one of those electron I've got an atom or a nucleus there ....
with an equal oposite positive charge make this material electrically neutral...
Now ...I do .... I just learn together for the moment...if I do p-type....
here we have excess holes and all we think of there is ...
that means there is a vacancy of electron where ?...in valence band.
There is no such thing as a hole.So electron we have electrons that are up in the conduction band...
that increase the conductivity or we have a vacancy or dc for a electron move in a vacancy in the valence band...
and that also....part of the sheet resistance to go down....for I introduce the material ....like a borron...
or from other material having three valence electron....into this area here...I have more open vacancy in my
crystal structure to electron free them move around and cause the resistivity also to decrease.
If I look at this ...it's also electrically neutral..
OK ! Now ...got .all of these hole over here all of these free hole ....got all of those free electron
when I put that too much area together some of the electron fall into the hole....wherein our electron
falls into a hole.....what it electrically behind on this side ?
It leaves behind fixed positively charged atom.
so ....leave behind fixed positive charge....
so this ends up all positive...(Micron : 4 minutes....)
OK...Over here now I'm gonna electron comming in I ends up causing this avenue electrically what ?
(....) Negative charge ....so we notice p-type electrically neutral over here....over here...I've got a negative charge...
over here...I've got a positive charge.
why don't all of the electron turn the n-type go over and fall into the hole on the p-side ?
(...) Yeah!....everytime I lose an electron here a fixed atoms left behind it...and there exisist an
electric field trying to pull that electrons back.....so they equalize the charge....
the thing we note here....is that when I lose my electron here and close up the hole over here ...
to deplete it over here electrons or the hole to deplete it free carriers here.....this is called depletion region
against(??) light two depletion capacitance and that's all we will talk about when we come back next time...
...there any last twenty second question ?
No?! all right see you for the quize of the begining of the class on Friday. Have a good one!
第四回めの講義はここまででした。
聴き取りは大変。
特に、自宅のPCの音声がつぶれかけていて余計わかりにくい・・・会社のPCはもっときれいな音声だった・・・
（ADSLなのでノイズが増えるのかもしれない？？それとも、VAIOのA/D、D/Aが低級なんだっけ？？？）
以上、ちょっと変態な作業でした・・・・
この後、同じＩＰでサーバーへのアクセスが出来なくなったので、まねはしませんように！
Jake Baker CMOS教科書
ネットレクチャーはこちら！Lecture notes and streaming videos をクリック！
基礎から固める人は↓
基礎から
Ｏｐアンプの設計から入る人は↓
詳しくアンプを設計
ディジタル信号処理の回路設計を知りたい人↓
Mixed Signal 設計
へそれぞれどうぞ！
