Now...
Notice one of big things that makes the difference between ... and logic design
they just put swiches together and somebody that really confidence in knowing
how to excuse the perfotmance sad of the chip is understanding parasitic symbol
So immediatellyyou see a p-substrate and you see there's n-well
and you notice there is a parasitic what ?...
yadiode.
it's parasitic because it's unwantedit's a part of the process.Now
note!....In CMOS
All pn junctions should be reverse biased.
You should never at the situation
unless you got a problem where you have a forward baised pn junction
that in general indicate something bad is happening.
So when we talk about these two layersit will often fade(?)
especially in this class are digital
the substrate is ground potential.
we don't know how to put it ground potential right now.
In N-wellmake it Vdd or something above ground.OK ?
And so that if they ask why you keep substrate groundand why you
keep N-well vdd your answer is ......
so I can ensure that ......
All right
Now
The next thing that we know islet me just comment a little quick on
how we make transition between layout that we draw and acutual fabrication here. OK?
So we draw a Box on an N-well layer
and on that we specifyyeah...above substrate down here
there's a p-substrate of which is bulk called what?
Wafer!
and above thatwe have the mask
and let you say
this is a positive mask.and on that mask
this is an opaque region here........
on each side.yathis is a opaque region.
this is a mask or a reticle.
and I think I covered this already but often times
now a daysthey will make sure this mask would be
5 times bigger than final size that they need
because the dimension of that final size are shrinking
they project the image down and it get reduced onto the wafer from a mask
that's larger a reticlethat's larger OK ?
So all .....right here
I draw my N-well in my layout program on this Boxsome location I don't know
It specify
heyI wanna put this mask in therethe N-well mask.
It ... openning where I have these Boxes.
Then I take lightan ultraviolet light source
and I shine light through this openning.Wellthe light can move through
not an opaque I don't have material ...make some the light go through
and is used on patterning my wafer.
So I generally do for an N-well process
.......
I will deposite a photo resist.And itphoto resist
is sensitive to light some sort of a polymerI believe
that characteristics change when it is exposed to UVlight
So when I shine the light through this mask
I have this area hereyeah...
and that getting it's characteristics changedphysically changed.
SonowI try done that I shine this...
I gotta photo resist on here were sections
where I'd drawn my N-well have been changed.
SoI haven't drawn my N-well yet. OK.
So...
I know the reticle is generally larger even on showing it one to one
the reticle is generally larger than final openning that I'm trying to make.
I know that have light hereand it's comming from UV light sourceor ultraviolet
and it's dimension shrink more than to a extream UV and ...getting shorter and shorter.
I know that when I have a mask
it appears that my entire waferespecially for a lager wafer like the...a 300mm or a 12inch wafer
I take this mask and I will expose different spots on the wafer
and I step it across ....
shine the light on this spotstep it overshine it right herestep it over
shine it right here...what's that ? called machine that...
moves the reticle around ?
Yeah Stepper ! So it steps aroundand so you could also say
Oh gee I'm gonna have the same exact chip we produced a number of times.
so like in a chip we made in this class we get for each time
for it's apprication we get five copies of our chipbecause it is a wafer....
OKIt steps across...actually it's more than that.
In any case it steps across a certain number of times to shine the light.
Here Is every body clear on this step ?
Soalways just from drawing a Box on the N-well layer...OK.
So now I'm gonna remove this part.
and I talk about this.
What I'll do next is I etch...etch away this material.
Sothis material goes awayand I end up with something look like this......
On my p-substrate I end up with getting a resist hereand resist here
and...I got the top of the wafer exposed.
So I've got the silicon bulk right here on the top exposed.
I mean either gona do an immplant or a diffusion which means I'm gonna appliy
and actually I'm drying this in a horizontal direction.
Most of the time when they do thiswafers are stucked in ...ahactually we'd gotta a picture
in the bookI'll show youthey are stucked in a boat...inlet see page...
but here is a good examplewe can zoom in on this
Here's a wafer in a oxidation furnace some sort of furnace a wafer is set up with right here
in the other area am...in this case oxidationbut if we had a diffusion furnace
we can use this to diffuse a wafer.you'd have a certain number of wafers going through
on one lod at a time that was fit in this diffusion furnace.
OK. Also I should point out that these processes here we take a light just exposed...
the light exposed you know shine down on it right here very quick.
there is no speed bottom we step the mask across we expose the wafer we just shine the light on it
for a certain time.
The issues here are the resolution that you can resolve we need to start doing the patterning
we...you can make much finer resolution if you use what's called EB ...sort of what we have
in a Lab here Boise State.However it goes through basically with electron beamand writes everything
nice and slow
so it's more than research tool than a production tool.
OKbut you can make a really small devices really useful for doing a research.
This is a first processall right.
So I expose the top of my wafer to a diffusion source.
and Let that does(?)...here I'm gonna expose to a diffusion source which is
sayphosphorous.
Nowsilicon has how many valence electrons ? It is four electrons on the outer orbital
that's a valence orbital. Phosphorous which is an N-type semiconductor has five
five valence electrons.
And what that does is in a longer lead allow that diffusion we heated up in a longer lead
allow it meltwhatever I wanna callinto the waferend up getting a area herewhich
counter dopes the p-substrate and ah...end up making this N-type.
Now I'm gonna comment on thisbecause I wanna everybody understand a few things at this point
but there is a lot actually that happens.
To change it to N-typeyou have to counter dope the p-substrate.
That means we have to take thiswhich is got to say borron with three velence electrons.
And you have to add an atom with four of that vallence electrons and an atom with five
valence electrons which fills up available p-typeyou know vacancies.
And it adds additional that kind ofcalled counter dope like I said.
Nowhere's ahyou knowif you remember from your basic electronicsthey say
OhPMOS device is generally slower than the NMOS devicebecause of electron mobility is higher than
the hole moblity.
...also a issue herescattering.
When you ...make... p ah... n-type implant
to your diffusionn-type hereyou counter dope you end up not having a
goot crystaline structure you end up getting more scattering and more defect.
So by conter doping you end up with by the holes more scattering and lower mobility
by itself. So even if the electron and hole mobilities are exactlly the same
the facton counter doping the p-type substrate is kind of....you end up...that I make...I'm gonna make
...assuming ifI know....I guess I should say that you make the PMOS device in the N-well
with all...some PMOS devices that(?) on it faster(?) than NMOS devices. OK? So to get around that people use what we call
twintab or a p-well process so just I just wanna briefly before we move on herewe'd made all the N-well
in order to suppose...?...before we move on I wanna comment on P-well process.
This is in a N-well process which is...we will use in our classwhich is ubiquitous in industry.
There's also a P-well process.
.....
Are you with us yet...Micron ?
.....
Yeah with youJake.
OK so you got a...
N-substrate we did the P-well...this this is our P-welland again the P-well goes the most negative potential
and N-substrate goes the most positive potentialbecause I...I always have it drawn how I don't have to think about it.
I draw my diode on that...all my parasitic pn junction should be reverse biased. This is a P-well process.and ah.....
N-sub....getting me better(?) because there's no counter doping in a N-substrate.My NMOS.....
My PMOS hereyou see a better parforming with PMOS devices.
Here on counter doping N-substrate with my PMOS
so my NMOS ...so in therethis is a bulk or a body
so I end up with a lower quality NMOS devices.
So you might ask Wellis the N-well avoid couter doping ?
And the answer is Yes you can use twintub process wellthis is a light N or P substrate and then you put .....
we will talk about this later...just...let's say this is...N-well1 and N-well2 that would be a light P this is P-well.
there's different flavour here anyway I just mentioned now I'll covered it again later...
Any question on counter doping ? a p-substrate parforming N-well ?
Are there any question on how went from the N-well to ....
how we went from the N-well layout to this structure right here?
OK.So.
I'd got some simple questions I'm gonna ask.
（この点に関しては、当たり前の話なので省略！）
Notice one of big things that makes the difference between ... and logic design
they just put swiches together and somebody that really confidence in knowing
how to excuse the perfotmance sad of the chip is understanding parasitic symbol
So immediatellyyou see a p-substrate and you see there's n-well
and you notice there is a parasitic what ?...
yadiode.
it's parasitic because it's unwantedit's a part of the process.Now
note!....In CMOS
All pn junctions should be reverse biased.
You should never at the situation
unless you got a problem where you have a forward baised pn junction
that in general indicate something bad is happening.
So when we talk about these two layersit will often fade(?)
especially in this class are digital
the substrate is ground potential.
we don't know how to put it ground potential right now.
In N-wellmake it Vdd or something above ground.OK ?
And so that if they ask why you keep substrate groundand why you
keep N-well vdd your answer is ......
so I can ensure that ......
All right
Now
The next thing that we know islet me just comment a little quick on
how we make transition between layout that we draw and acutual fabrication here. OK?
So we draw a Box on an N-well layer
and on that we specifyyeah...above substrate down here
there's a p-substrate of which is bulk called what?
Wafer!
and above thatwe have the mask
and let you say
this is a positive mask.and on that mask
this is an opaque region here........
on each side.yathis is a opaque region.
this is a mask or a reticle.
and I think I covered this already but often times
now a daysthey will make sure this mask would be
5 times bigger than final size that they need
because the dimension of that final size are shrinking
they project the image down and it get reduced onto the wafer from a mask
that's larger a reticlethat's larger OK ?
So all .....right here
I draw my N-well in my layout program on this Boxsome location I don't know
It specify
heyI wanna put this mask in therethe N-well mask.
It ... openning where I have these Boxes.
Then I take lightan ultraviolet light source
and I shine light through this openning.Wellthe light can move through
not an opaque I don't have material ...make some the light go through
and is used on patterning my wafer.
So I generally do for an N-well process
.......
I will deposite a photo resist.And itphoto resist
is sensitive to light some sort of a polymerI believe
that characteristics change when it is exposed to UVlight
So when I shine the light through this mask
I have this area hereyeah...
and that getting it's characteristics changedphysically changed.
SonowI try done that I shine this...
I gotta photo resist on here were sections
where I'd drawn my N-well have been changed.
SoI haven't drawn my N-well yet. OK.
So...
I know the reticle is generally larger even on showing it one to one
the reticle is generally larger than final openning that I'm trying to make.
I know that have light hereand it's comming from UV light sourceor ultraviolet
and it's dimension shrink more than to a extream UV and ...getting shorter and shorter.
I know that when I have a mask
it appears that my entire waferespecially for a lager wafer like the...a 300mm or a 12inch wafer
I take this mask and I will expose different spots on the wafer
and I step it across ....
shine the light on this spotstep it overshine it right herestep it over
shine it right here...what's that ? called machine that...
moves the reticle around ?
Yeah Stepper ! So it steps aroundand so you could also say
Oh gee I'm gonna have the same exact chip we produced a number of times.
so like in a chip we made in this class we get for each time
for it's apprication we get five copies of our chipbecause it is a wafer....
OKIt steps across...actually it's more than that.
In any case it steps across a certain number of times to shine the light.
Here Is every body clear on this step ?
Soalways just from drawing a Box on the N-well layer...OK.
So now I'm gonna remove this part.
and I talk about this.
What I'll do next is I etch...etch away this material.
Sothis material goes awayand I end up with something look like this......
On my p-substrate I end up with getting a resist hereand resist here
and...I got the top of the wafer exposed.
So I've got the silicon bulk right here on the top exposed.
I mean either gona do an immplant or a diffusion which means I'm gonna appliy
and actually I'm drying this in a horizontal direction.
Most of the time when they do thiswafers are stucked in ...ahactually we'd gotta a picture
in the bookI'll show youthey are stucked in a boat...inlet see page...
but here is a good examplewe can zoom in on this
Here's a wafer in a oxidation furnace some sort of furnace a wafer is set up with right here
in the other area am...in this case oxidationbut if we had a diffusion furnace
we can use this to diffuse a wafer.you'd have a certain number of wafers going through
on one lod at a time that was fit in this diffusion furnace.
OK. Also I should point out that these processes here we take a light just exposed...
the light exposed you know shine down on it right here very quick.
there is no speed bottom we step the mask across we expose the wafer we just shine the light on it
for a certain time.
The issues here are the resolution that you can resolve we need to start doing the patterning
we...you can make much finer resolution if you use what's called EB ...sort of what we have
in a Lab here Boise State.However it goes through basically with electron beamand writes everything
nice and slow
so it's more than research tool than a production tool.
OKbut you can make a really small devices really useful for doing a research.
This is a first processall right.
So I expose the top of my wafer to a diffusion source.
and Let that does(?)...here I'm gonna expose to a diffusion source which is
sayphosphorous.
Nowsilicon has how many valence electrons ? It is four electrons on the outer orbital
that's a valence orbital. Phosphorous which is an N-type semiconductor has five
five valence electrons.
And what that does is in a longer lead allow that diffusion we heated up in a longer lead
allow it meltwhatever I wanna callinto the waferend up getting a area herewhich
counter dopes the p-substrate and ah...end up making this N-type.
Now I'm gonna comment on thisbecause I wanna everybody understand a few things at this point
but there is a lot actually that happens.
To change it to N-typeyou have to counter dope the p-substrate.
That means we have to take thiswhich is got to say borron with three velence electrons.
And you have to add an atom with four of that vallence electrons and an atom with five
valence electrons which fills up available p-typeyou know vacancies.
And it adds additional that kind ofcalled counter dope like I said.
Nowhere's ahyou knowif you remember from your basic electronicsthey say
OhPMOS device is generally slower than the NMOS devicebecause of electron mobility is higher than
the hole moblity.
...also a issue herescattering.
When you ...make... p ah... n-type implant
to your diffusionn-type hereyou counter dope you end up not having a
goot crystaline structure you end up getting more scattering and more defect.
So by conter doping you end up with by the holes more scattering and lower mobility
by itself. So even if the electron and hole mobilities are exactlly the same
the facton counter doping the p-type substrate is kind of....you end up...that I make...I'm gonna make
...assuming ifI know....I guess I should say that you make the PMOS device in the N-well
with all...some PMOS devices that(?) on it faster(?) than NMOS devices. OK? So to get around that people use what we call
twintab or a p-well process so just I just wanna briefly before we move on herewe'd made all the N-well
in order to suppose...?...before we move on I wanna comment on P-well process.
This is in a N-well process which is...we will use in our classwhich is ubiquitous in industry.
There's also a P-well process.
.....
Are you with us yet...Micron ?
.....
Yeah with youJake.
OK so you got a...
N-substrate we did the P-well...this this is our P-welland again the P-well goes the most negative potential
and N-substrate goes the most positive potentialbecause I...I always have it drawn how I don't have to think about it.
I draw my diode on that...all my parasitic pn junction should be reverse biased. This is a P-well process.and ah.....
N-sub....getting me better(?) because there's no counter doping in a N-substrate.My NMOS.....
My PMOS hereyou see a better parforming with PMOS devices.
Here on counter doping N-substrate with my PMOS
so my NMOS ...so in therethis is a bulk or a body
so I end up with a lower quality NMOS devices.
So you might ask Wellis the N-well avoid couter doping ?
And the answer is Yes you can use twintub process wellthis is a light N or P substrate and then you put .....
we will talk about this later...just...let's say this is...N-well1 and N-well2 that would be a light P this is P-well.
there's different flavour here anyway I just mentioned now I'll covered it again later...
Any question on counter doping ? a p-substrate parforming N-well ?
Are there any question on how went from the N-well to ....
how we went from the N-well layout to this structure right here?
OK.So.
I'd got some simple questions I'm gonna ask.
（この点に関しては、当たり前の話なので省略！）
